Open source

Projects we maintain for the analog community.

Schemify is our one closed-source product. Its plugin interface and file format are open source, and so is everything on this page.

We build these because the analog community has given us a lot. Use them with Schemify or without it.

Open
Everything on this page
Closed
Schemify itself
Open
Schemify’s plugin interface and file format

Funded by the people who use them

A small team maintains these projects, and sponsors pay for part of that work. If they save you time, you can help keep them going.

Sponsor on GitHub

Monthly or one-off, as an individual or a company.

Become a sponsor

Sponsor with an invoice

Companies that need an invoice can email us. GitHub charges 3% on invoiced sponsorships.

sponsors@scouren.com

Sponsors

Your logo hereYour logo hereYour logo hereYour logo here

Schemify ecosystem

The open parts of Schemify, and plugins built on them.

  • Schemify SDK

    The file format, plugin ABI, SDKs and sandbox host for building Schemify plugins and themes.

    RustMIT★ 0no release

  • Gm&IdW

    A gm/Id design visualiser: gmid.* sizing functions for docs pages.

    RustMIT★ 0no release

  • Interoperate

    Import and export with xschem and Virtuoso, so Schemify can sit beside the editor your team uses.

    RustMIT★ 0no release

  • Schemify-Themes

    16 themes and 115 colour schemes, ported from spicetify’s catalogue.

    Pythonlicence unstated★ 0no release

Simulation

A SPICE engine and the Verilog-AMS compiler behind its models.

  • ESpice

    A SPICE simulator in Zig that reads ngspice, HSPICE and Spectre decks. Every device model is Verilog-A, compiled by VerA.

    espice -r out.raw deck.sp

    Benchmarks coming with each release.

    Language
    Zig
    Licence
    Apache-2.0
    Stars
    0
    Latest release
    none yet

  • VerA

    A Verilog-AMS compiler with SIMD and GPU support. It emits Zig device code with exact Jacobians, or an OSDI 0.4 library for ngspice.

    vera --emit-zig model.va -o device.zig

    Benchmarks coming with each release.

    Language
    Zig
    Licence
    Apache-2.0
    Stars
    1
    Latest release
    v0.23.0

Verification

Physical verification you can gate CI on.

  • GPurify

    DRC, LVS, ERC and PEX in one engine, on the CPU or the GPU, with decks for sky130, GF180MCU, IHP SG13G2 and ASAP7. Each rule reports whether it ran.

    gpurify drc layout.gds --deck sky130

    Benchmarks coming with each release.

    Language
    Zig
    Licence
    MIT
    Stars
    0
    Latest release
    none yet

Project setup and standards

Starting a block, and keeping tools honest.

  • AMTemplate

    A template for analog and mixed-signal ASIC design on open tools: make targets and pinned Nix shells for each block, up to tapeout.

    Makefileno licence file★ 0no release

  • Conformance Suite

    A conformance suite for Verilog-AMS, Verilog-A and IEEE 1364, run against any tool by one harness.

    C harnessno licence file★ 0no release

Stars and releases as of 7 November 2026.